logical state中文是什么意思

發音:

中文翻譯
造句

邏輯狀態

logical adj. 1.邏輯的，邏輯上的；邏輯學上的。 2.合乎邏 ...
state n. 1.〔常作 S-〕國，國家；〔通例作 S-〕(美國 ...
be logical 合乎邏輯
logical adj. 1.邏輯的，邏輯上的；邏輯學上的。 2.合乎邏輯的。 3.邏輯上必然的。 logical constants 邏輯常詞[常項]。 logical necessity 邏輯的必然性。 a logical argument 條件分明的論證。 a logical process 合理的程序，合乎邏輯的[必然的]過程。 the logical result 必然的結果。 adv. -ly ,-ness n.
logical and 邏輯與
logical if 邏輯若
logical not 邏輯非
logical or 邏輯或
logical-in 邏輯歸入
the logical 合選輯之歌
in a state 處于糟糕、混亂或不整潔的狀態
in a state of 處于……的狀態
in state 本州的; 正式地, 莊重地
on state 導通狀態; 接通的; 通態
state‘s will 國家意志
will of the state 國家意志
a logical impossibility 邏輯上不可能的事
a logical mind 善于推理的頭腦
add, logical 邏輯加
architecture, logical 邏輯（體系）結構
boolean-logical 布爾邏輯的
compare logical 比較邏輯
connective logical 邏輯連接號
infra-logical 邏輯下的

"查查詞典"手機版

千萬人都在用的超大詞匯詞典翻譯APP

例句與用法

To change a physical or logical state to its opposite
將一種物理狀態或邏輯狀態變成它的相反的狀態。
Flags may have one of two logical states , true or false . programs that use flags as arithmetic operands have an environmental dependency
旗標可以有兩個邏輯狀態之一,真或假.使用旗標作為計算操作的程式有環境相依性
By exploring the characters of dynamic power supply currents of digital circuits using spice , this paper analyzed the relation between iddt and the switching activities when a circuit changes from one logical state to another
本文通過spice實驗研究數字電路動態電流的特性，分析了數字電路的動態電流與電路邏輯狀態轉變之間的關系。
While programs in the java language are theoretically immune from " memory leaks , " there are situations in which objects are not garbage collected even though they are no longer part of the program s logical state
雖然用java語言編寫的程序在理論上是不會出現“內存泄漏”的，但是有時對象在不再作為程序的邏輯狀態的一部分之后仍然不被垃圾收集。
The thesis also introduces the virtual instrument ’ s concept , system architecture , etc . the development of virtual instrument ’ s application software is discussed in detail . it includes virtual instrument software architecture ( visa ) , and virtual instrument ’ s software platforms . the thesis discusses the principle and mechanism of work of the simulation of embedded system . by comparing with the principle of traditional logical analyzer , it draw a conclusion that the virtual logical analyzer will work in synchronous way when it is used for both logical state analyzer and logical time analyzer . the thesis
論文接著探討了嵌入式仿真平臺的原理和工作機制,通過與傳統邏輯分析儀原理的比較,得出了嵌入式仿真平臺下邏輯分析儀無論是做定時分析,還是做狀態分析都工作在同步方式下;并重點剖析了探頭原理,采樣定理和毛刺,數據的建立和保持時間等邏輯分析儀的重要技術指標,得出了虛擬環境對虛擬邏輯分析儀的功能和各項技術指標的影響,還提出了流水線狀態表的思想和實現機制。
In addition to the normal functional interface of a component , by adding a test interface that exposes the logical states of the component , a tester can dynamically monitor and capture states information and service calling sequence of the component during testing
更進一步，在進行組件集成測試時，本文提出了組件內置測試機制和一種提高組件可測試性的方法，通過對各交互組件進行封裝并擴展測試接口，達到在測試時動態監視和捕捉組件狀態和服務調用序列信息的作用。